1. Field of the Invention
The present invention relates to a semiconductor integrated circuit capable of facilitating layout modification involved in changes of circuit components of the semiconductor integrated circuit.
2. Description of Related Art
Conventionally, as for the chip layout of a semiconductor integrated circuit such as a microcomputer, ASIC (Application Specific Integrated Circuit) and the like, a matter of highest priority is to minimize the chip cost by reducing the chip area as much as possible. More specifically, the layout (floor plan) of integrated circuits constituting chips and sub-modules such as pad cells is usually optimized from the view point of minimizing the chip area under conditions that the timing constraints of interface signals are satisfied. Here, the integrated circuits constituting chips are such as a CPU, ROM, RAM, timer, and UART (Universal Asynchronous Receiver Transmitter).
In addition, as for one-chip microcomputers with a built-in ROM and RAM, a plurality of serialized products are often developed by varying the size of the ROM and RAM or by making variations in peripheral circuits. In such one-chip microcomputers, the layout is also carried out in terms of minimizing the chip area.
In the foregoing layout modification of the semiconductor integrated circuit considering only minimizing the chip area, the layout of the entire circuit must be changed every time the function or performance of the circuit components varies. This presents a problem of requiring a lot of labor for making the layout modification involved in the changes of the circuit components.
To solve the problem, a technique is provided that separates the entire circuit into two section, a rather fixed section whose functions are seldom modified, and a rather extendable, modifiable section whose functions are easily added or modified, and that places the two sections separately in the vertical or horizontal direction (see, relevant reference 1).
[Relevant Reference 1]
                Japanese patent application laid-open No. 61-190969        
To change the circuit components of the semiconductor integrated circuit, the conventional method has a problem in that it must modify the entire layout in such a manner that the chip area becomes minimum, and that it must carry out the characteristic evaluation of the entire circuit once more. Accordingly, it requires much development manpower for the chip layout design and the verification and evaluation of the characteristics involved in the modification of the circuit components.
On the other hand, the technique disclosed in the relevant reference 1 carries out the layout design of the rather fixed section and that of the extendable, modifiable section separately without considering the verification and evaluation of the circuit characteristics. Consequently, it is likely that the characteristic verification and evaluation of the entire circuit after the layout modification must be made once again, which can present a problem of being unable to reduce the manpower required for the modification of the circuit components.